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ADC390

ADC Module, 2-Channels 170MSPS @ 12bits; 400MB/sec Digital Bus Interface; Xilinx Virtex II FPGA

Overview | Features | Benefits | Layout | Block Diagram

Overview

ADC390 is the ultimate ADC Module and offers a dual channel solution at 210MSPS conversation rate at 12-bits. The single width Module has two AD9430s from Analog Device Inc. rate and these are optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including track-and-hold (T/H) and reference are included on the chip to provide a complete conversion solution. They are interfaced to a Xilinx Virtex-2 FPGA that controls the ADC converters and also provide the data-route of the converted analogue signals.

The data are routed to four 16-bit Digital Buses, using two 400MB/sec Digital Bus connectors and the control of the ADCs are done with the help of a Comm-Port (the 8-bit data parallel inter-processor ports of the 'C4x processor).

Key Features:

	Two 12-bit ADCs (AD9430 sampling up to 210 MHz using LVDS interface.
	Single width module.
	Two 400MB/sec Digital Bus connectors.
	Two 20 Mbytes/s communication ports.
	Low-jitter system clock.
	Xilinx Virtex-II FPGA (XC2V1000-6).
	On-board PROM (Xilinx XC17V08) loads up the default configuration into the FPGA
	50-Ohm analogue inputs and outputs, external triggers and clocks via MMBX (Huber and Suhner) connectors.
	User defined pins for external connections.
	Compatible with a wide range of 400MB/sec Digital Bus modules.
	TIM standard compatible.
	12 months warranty

Benefits

	Ideal for flexible Wireless and Wired Broadband Communications Systems, Cable Reverse Path Solutions, Communications Test Equipment, Radar and Satellite Subsystems and Power Amplifier Linearization and similar type of application.
	The XC2V1000 Xilinx FPGA has 1 million gates and we use approx. half a million for controlling the converters and rest can be used by the OEM customer for doing pre-processing on the data or for other custom controls.
	The ADC390 has more than 40 free I/O pins for either 'InterModule' communications or for custom applications/use.

Layout for the ADC390 (PDF):

CLICK for Block Diagram (PDF):

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